IT8673F View Datasheet(PDF) - ITE Tech. INC.
Part Name
Description
MFG CO.
'IT8673F' PDF : 128 Pages View PDF
IT8673F
If bit 1 is set, ECP mode is enabled. If bit 0 is set, EPP mode is enabled. These two bits are
independent. However, according to the EPP spec., when Parallel Port Primary Base Address bit 2
is set to 1, the EPP mode cannot be enabled.
10.8 FAN Controller Configuration Registers (LDN=04h)
10.8.1 FAN Controller Activate Register (Index=30h, Default=00h)
Bit
7-1 Reserved
FAN Controller Enabled.
0
1: Enabled.
0: Disabled.
Description
10.8.2 FAN Controller Base Address MSB Register (Index=60h, Default=00h)
Bit
Description
7-4 Read only as “0h” for Base Address[15:12].
3-0 Read/write, mapped as Base Address[11:8].
10.8.3 FAN Controller Base Address LSB Register (Index=61h, Default=80h)
Bit
Description
7-3 Read/write, mapped as Base Address[7:3].
2-0 Read only as “000b”.
10.8.4 PME# Direct Access Base Address MSB Register (Index=62h, Default=02h)
Bit
Description
7-4 Read only as “0h” for Base Address[15:12].
3-0 Read/write, mapped as Base Address[11:8].
10.8.5 PME# Direct Access Base Address LSB Register (Index=63h, Default=00h)
Bit
Description
7-3 Read/write, mapped as Base Address[7:3].
2-0 Read only as “000b”.
10.8.6 FAN Controller Interrupt Level Select (Index=70h, Default=09h)
Bit
Description
7-4 Reserved with default “0h”.
3-0 Select the interrupt level note1 for FAN Controller.
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