JS28F128P30BF65A View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
JS28F128P30BF65A
Numonyx -> Micron
'JS28F128P30BF65A' PDF : 90 Pages View PDF
P30-65nm SBC
15.3
AC Read Specifications
Table 25: AC Read Specifications (Sheet 1 of 2)
Num
Symbol
Parameter
Asynchronous Specifications
R1
tAVAV
Read cycle time
Easy BGA/QUAD+
TSOP
R2
tAVQV
Address to output valid
Easy BGA/QUAD+
TSOP
R3
tELQV
CE# low to output valid
Easy BGA/QUAD+
TSOP
R4
R5
R6
R7
R8
R9
R10
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or OE#
change
R11
tEHEL
CE# pulse width high
R12
tELTV
CE# low to WAIT valid
R13
tEHTZ
CE# high to WAIT high-Z
R15
tGLTV
OE# low to WAIT valid
R16
tGLTX
OE# low to WAIT in low-Z
R17
tGHTZ
OE# high to WAIT in high-Z
Latching Specifications
R101
R102
R103
tAVVH
tELVH
tVLQV
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
Easy BGA/QUAD+
TSOP
R104
tVLVH
R105
tVHVL
R106
tVHAX
R108
tAPA
R111
tPHVH
Clock Specifications
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
RST# high to ADV# high
R200
fCLK
CLK frequency
Easy BGA/QUAD+
TSOP
R201
tCLK
CLK period
Easy BGA/QUAD+
TSOP
R202
tCH/CL
CLK high/low time
Easy BGA/QUAD+
TSOP
R203
tFCLK/RCLK
CLK fall/rise time
Min
65
75
-
-
-
-
-
-
0
0
-
-
0
17
-
-
-
0
-
10
10
-
-
10
10
9
-
30
-
-
19.2
25
5
9
0.3
Max
-
-
65
75
65
75
25
150
-
-
20
15
-
-
17
20
17
-
20
-
-
65
75
-
-
-
25
-
52
40
-
-
-
-
3
Unit Notes
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
1,2
ns
1
ns
1,3
ns
1,2,3
ns
ns
1,3
ns
ns
1
ns
ns
1,3
ns
1
ns
1,3
ns
ns
ns
ns
1
ns
ns
ns
ns
1,4
ns
1
ns
MHz
MHz
ns
ns
ns
ns
ns
1,3,5,6
Datasheet
50
Apr 2010
Order Number: 208033-02
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