K4B2G1646C-HCF8 View Datasheet(PDF) - Samsung
Part Name
Description
MFG CO.
'K4B2G1646C-HCF8' PDF : 64 Pages View PDF
K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIS
tIH
CK
CK
DQS
tIS tIH
DQS
VDDQ
tDS tDH
VIH(AC) min
VREF to ac
region
VIH(DC) min
VREF(DC)
VIL(DC) max
nominal slew
rate
VIL(AC) max
VSS
tVAC
tDS tDH
tVAC
nominal
slew rate
VREF to ac
region
∆ TF
Setup Slew Rate
Falling Signal
=
VREF(DC) - VIL(AC)max
∆ TF
∆ TR
Setup Slew Rate
Rising Signal
=
VIH(AC)min - VREF(DC)
∆ TR
Figure 21. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
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