KB2511B View Datasheet(PDF) - Samsung
Part Name
Description
MFG CO.
'KB2511B' PDF : 35 Pages View PDF
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
KB2511B
EW
EWOUT = 2.5V + K1 ( VOUT - VDCMID )2 + K2 ( VOUT - VDCMID )
K1 is adjustable by EW amplitude I2C register
K2 is adjustable by keystone I2C register
Dynamic horizontal phase control
IOUT = K3 ( VOUT - VDCMID ) 2 + K4 ( VOUT - VDCMID )
K4 is adjustable by side pin balance I2C register
K3 is adjustable by parallelogram I2C register.
Function
When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an
external capacitor, COSC = 150nF, the typical free running frequency is 100Hz.
Typical free running frequency can be calculated by:
f0
(Hz)=
1.5•10-5
•
1
COSC
A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can syn-
chronise the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor connected on
pin 22. A capacitor in the range [150nF, 220nF] ± 5% is recommanded for application in the following range: 50Hz
to 165Hz.
Typical maximum and minimum frequency, at 25°C and without any correction (S correction or C correction), can
be calculated by:
f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0
If S or C corrections are applied, these values are slighty affected.
If a synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more con-
stant. An internal correction is activated to adjust it in less than a half a second : the highest voltage of the ramp pin
22 is sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance ampli-
fier generates the charge current of the capacitor. The ramp amplitude becomes again constant.
The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations.
It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory.
Good stability of the internal closed loop is reached by a 470nF ± 5% capacitor value on pin 20 (VAGC)
31
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