KB2514 View Datasheet(PDF) - Samsung
Part Name
Description
MFG CO.
'KB2514' PDF : 55 Pages View PDF
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Registers
Frame Control
Registers - 1
(Row15,
Column01)
Table 11. Register Description(Continued)
Bits
CH5 ~ CH0
(Bit 5 ~ 0)
VPOL
(Bit 6)
HPOL
(Bit 7)
dot1, dot0
(Bit 9, 8)
Description
Character height control
While the purpose of VZ[1:0] (vertical character height) is to control the
absolute size of the character, the purpose of CH[5:0] (Character Height) is
to output OSD of a uniform size even if the resolution changes. If you adjust
the value in the range of CH = 18 ~ CH = 63, each line's repeating number
is decided (standard height CH = 18 is the reference value), by which the
line is repeated. For more information on repeating number selection, refer
to character height.
Polarity of vertical fly back signal
If this bit is '1', VFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
Polarity of horizontal fly back signal
If this bit is '1', HFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
Resolution control (dots/line)
Dot1 Dot0
No. of Dots
0
0
320 dots/line
0
1
480 dots/line
1
0
640 dots/line
1
1
800 dots/line
HF2~HF0
(Bit C ~ A)
FPLL
(Bit D)
As shown above, the number of dots per horizontal line is decided by a
combination of these two bits.
Horizontal frequency
PLL's horizontal frequency is decided by the combination of these 3 bits.
This is related to the selection of DOT[1:0], so you can't numerically
express the frequency range with only the HF[2:0] selection. For more
information, please refer to HF Bits Selection.
Full range PLL
If this bit is '1', the OSD_PLL block's VCO operates at full range (4.8MHz -
96MHz). If it is '0', it operates within the region decided by the HF bit [C:A]
explained above. if you can’t optimize OSD screen decided by the HF bit in
the high region, you may set the FPLL bit to '1'.
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