KSZ8051MLL View Datasheet(PDF) - Micrel
Part Name
Description
MFG CO.
'KSZ8051MLL' PDF : 51 Pages View PDF
Micrel, Inc.
KSZ8051MLL
NAND Tree Support
The KSZ8051MLL provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND
tree is a chain of nested NAND gates in which each KSZ8051MLL digital I/O (NAND tree input) pin is an input to one
NAND gate along the chain. At the end of the chain, the CRS pin provides the output for the nested NAND gates.
The NAND tree test process includes:
• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving low each NAND tree input pin sequentially per the NAND tree pin order
• Checking the NAND tree output to ensure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 5 lists the NAND tree pin order.
Pin Number
18
19
20
21
22
23
27
28
29
32
33
34
35
36
38
39
42
43
40
41
Pin Name
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
RXDV
RXC
RXER
INTRP
TXC
TXEN
TXD0
TXD1
TXD2
TXD3
LED0
LED1
COL
CRS
NAND Tree
Description
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Table 5. NAND Tree Test Pin Order – for KSZ8051MLL
July 2010
23
M9999-071210-1.0
Share Link: 
