KSZ8051MLL View Datasheet(PDF) - Micrel
Part Name
Description
MFG CO.
'KSZ8051MLL' PDF : 51 Pages View PDF
Micrel, Inc.
KSZ8051MLL
NAND Tree I/O Testing
The following procedure can be used to check for faults on the KSZ8051MLL digital I/O pin connections to the board:
1. Enable NAND tree mode by either hardware pin strapping (NAND_Tree#, pin 32) or software (register 16h, bit 5).
2. Use board logic to drive all KSZ8051MLL NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, per KSZ8051MLL NAND Tree pin order, as follow:
a. Toggle the first pin (MDIO) from high to low, and verify the CRS pin switch from low to high to indicate
that the first pin is connected properly.
b. Leave the first pin (MDIO) low.
c. Toggle the second pin (MDC) from high to low, and verify the CRS pin switch from high to low to indicate
that the second pin is connected properly.
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Toggle the third pin (RXD3) from high to low, and verify the CRS pin switch from low to high to indicate
that the third pin is connected properly.
f. Continue with this sequence until all KSZ8051MLL NAND tree input pins have been toggled (tested).
Each KSZ8051MLL NAND tree input pin must cause the CRS output pin to toggle high-to-low or low-to-high to indicate a
good connection. If the CRS pin fails to toggle when the KSZ8051MLL input pin toggles from high to low, the input pin has
a fault.
July 2010
24
M9999-071210-1.0
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