L4990 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L4990' PDF : 24 Pages View PDF
L4990 - L4990A
Figure25.Turn-on and turn-offspeeds adjustment
Rg’
VCC
8
13V
DRIVE &
CONTROL
VC
9 (V)
17
13
10
OUT
L4990
D97IN497A
11
PGND
Rg(ON)=Rg+Rg’
Rg(OFF)=Rg
Rg
”Hiccup” keeps the system in control in case of
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (from A to C). Other external protection cir-
cuits are needed if a better control of overloads is
required.
delivers a voltage internally clamped, as shown in
fig. 25. Thus it is possible to supply the driver (pin
9) with higher voltages without any problem of
damage for the gate oxide of the external MOS,
but, of course, the power dissipation on the IC will
increase.
In UVLO conditions an internal circuit (shown in
fig.26) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from VCC = 0V up to the start-up threshold.
When the threshold is exceeded and the L4990
starts operating, VREFOK is pulled high (refer to
fig. 26) and the circuit is disabled.
It is then possible to omit the ”bleeder” resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Figure 26. Pull-Down of the output in UVLO.
Pin 8. VCC (Controller Supply). This pin supplies
the signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the current consumption is extremely low.
An internal Zener limits the voltage on VCC to
25V. Below this value the IC current consumption
is low but increases considerably if this limit is ex-
ceeded.
A small film capacitor between this pin and SGND
(pin 12), placed as close as possible to the IC, is
recommended to filter high frequency noise.
Pin 9. VC (Supply of the Power Stage). It sup-
plies the driver of the external switch and there-
fore absorbs a pulsed current. Thus it is recom-
mended to place a buffer capacitor (towards
PGND, pin 11, as close as possible to the IC)
able to sustain these current pulses and in order
to avoid them inducing disturbances.
This pin can be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 25,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
MOS. At turn-on the gate resistance is Rg + Rg’
and turn-off is Rg only.
Pin 10. OUT (Driver Output). This pin is the out-
put of the driver stage of the external power
switch. Usually, this will be a PowerMOS, al-
though the driver is powerful enough to drive
BJT’s (1.6A source, 2A sink, peak).
The driver is made up of a totem pole with a high-
side NPN Darlington and a low-side VDMOS, and
12/24
VREFOK
OUT
10
12
SGND
D97IN538
Pin 11. PGND (Power Ground). The current loop
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
Pin 12. SGND (Signal Ground). This ground ref-
erences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
Pin 13. ISEN (Current Sense). This pin is to be
connected to the ”hot” lead of the current sense
resistor Rsense (being the other one grounded), to
get a voltage ramp which is an image of the cur-
rent of the switch, (IQ). When this voltage is equal
to:
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