L4990 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L4990' PDF : 24 Pages View PDF
V13pk
=
IQpk⋅
Rsense
=
(VCOMP
3
−
1.4)
(8)
the conduction of the switch is terminated.
Figure 27. Internal LEB
L4990 - L4990A
To increase the noise immunity, a ”Leading Edge
Blanking” of about 100ns is internally realized as
shown in fig. 27. Because of that, the smoothing
RC filter between this pin and Rsense could be re-
moved or, at least, considerably reduced.
I
13
ISEN
1.2V
2V
3V
+
0
-
CLK
FROM E/A
PWM
+ COMPARATOR
-
+
-
OVERCURRENT
COMPARATOR
TO PWM
LOGIC
TO FAULT
LOGIC
D97IN503
Pin 14. DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessary to pull VCC (IC supply volt-
age, pin 8) below the UVLO threshold to allow the
device to restart. When disabled, the current con-
sumption of the IC is as low as before start-up.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
28. It is also possible to realize an overvoltage
protection, as shown in the section ” Application
Ideas”.
If used, bypass this pin to ground with a filter ca-
pacitor to avoid spurious activation due to noise
spikes. If not, it is advisable to connect the pin to
SGND, even though it might be left floating.
Pin 15. DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
mately,
Dx
≅
RT
RT
+ 230
(9)
if DC-LIM is grounded or left floating. Instead,
connecting DC-LIM to VREF (half duty cycle op-
tion), Dx will be set approximately to:
Dx
≅
2
⋅
RT
RT +
260
(10)
Figure 28. Disable (Latched)
DISABLE
SIGNAL
DIS
C
14
+
-
2.5V
D
DISABLE
Q
R
UVLO
D97IN502
and the output switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram, fig. 1) is acti-
vated. Fig. 29 shows the operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor CT (in order to get
duty cycles as close as possible to 50%) so the
oscillator frequency - with the same RT and CT -
will be slightly higher.
The halving of frequency can be used to reduce
losses at light load in all those systems that must
comply with requirements regarding energy con-
sumption (e.g. monitor displays).
13/24
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