DEVICES INCORPORATED
FIGURE 4C. FTAB = 1, FTF = 0
From
To
Clock
©F
A, B
© Other
C0
© Other
S4-S0
© Other
A, B
Setup time
C0
Setup time
S4-S0
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
L4C383
16-bit Cascadable ALU (Extended Set)
Calculated Specification Limit
= Same as 16-bit case
= (A, B © C16) + (C0 © Out)
= (C0 © C16) + (C0 © Out)
= (S4-S0 © C16) + (C0 © Out)
= (A, B © C16) + (C0 Setup time)
= (C0 © C16) + (C0 Setup time)
= (S4-S0 © C16) + (C0 Setup time)
= Same as 16-bit case
= (Clock © C16) + (C0 Setup time)
MOST
SIGNIFICANT
SLICE
A31-A16
B31-B16
A
B
F
C0
D
Q
16
CLOCK
F31-F16
A15-A0
B15-B0
A
B
C16
F
C0
C0, S4–S 0
D
Q
16
F15-F0
CLOCK
LEAST
SIGNIFICANT
SLICE
FIGURE 4D. FTAB = 1, FTF = 1
From
To
A, B
©F
A, B
© Other
C0
C0
S4-S0
S4-S0
©F
© Other
©F
© Other
A, B
Setup time
C0
Setup time
S4-S0
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
MOST
SIGNIFICANT
SLICE
A31-A16
B31-B16
A
B
F
C0
16
F31-F16
Calculated Specification Limit
= (A, B © C16) + (C0 © F)
= (A, B © C16) + (C0 © Out)
= (C0 © C16) + (C0 © F)
= (C0 © C16) + (C0 © Out)
= (S4-S0 © C16) + (C0 © F)
= (S4-S0 © C16) + (C0 © Out)
= (A, B © C16) + (C0 Setup time)
= (C0 © C16) + (C0 Setup time)
= (S4-S0 © C16) + (C0 Setup time)
= Same as 16-bit case
= (Clock © C16) + (C0 Setup time)
A15-A0
B15-B0
A
B
C16
F
C0
16
F15-F0
C0, S4–S 0
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
4
08/16/2000–LDS.383-E