L5987
6.4.1
Application information
The transfer function on the LC filter is given by:
Equation 17
where:
GLCs = -1----+------2-----------------1------Q--s--+-----------2------f-----L---------C-----------f-s+---z------E------S-2-----------R-----------s------f----L------C--------2-
Equation 18
fLC
=
-----------------------------------1------------------------------------
2 L COUT 1 + -R-E---O-S---U-R---T-
fzESR = 2------------E----S-----R1---------C----O----U----T-
Equation 19
Q = -----R----O----U--L--T--+-----CL-----O---C-U----TO----U---RT----O----U--R--T---O----U-E---T--S--+--R---E----S----R------,
ROUT = V--I--O-O---U-U--T-T--
As seen in Section 5.3 on page 12 two different kinds of network can compensate the loop.
In the two following paragraph the guidelines to select the type II and type III compensation
network are illustrated.
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the DC error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency higher than the desired bandwidth (that is: 2ESR COUT < 1 / BW), the type
III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (< 1 m), with very high frequency zero, so type III network is adopted to compensate
the loop.
In Figure 11 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:
Equation 20
fZ1 = -2-----------C-----3------1---R-----1----+-----R----3----
fZ2 = -2-----------R--1---4-------C----4-
Equation 21
fP0 = 0
fP1 = 2------------R--1---3-------C----3-
fP2 = 2------------R-----4----1----C-C-------4--4------+--------C--C--------5--5--
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