L6000 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6000' PDF : 24 Pages View PDF
L6000
PROGRAMMABLE FILTER CHARACTERISTICS(continued)
Symbol
EOUT
IO-
IO+
RO
Parameter
Output Noise Voltage
Differentiated Output
Output Noise Voltage Normal
Output
Output Noise Voltage
Differentiated Output
Output Noise Voltage Normal
Output
Filter Output Sink Current
Filter Output Source Current
Filter Output resistance Single
Ended
Test Condition
BW = 100MHz, Rs = 50Ω
FC = 18MHz, DACS = 0
BW = 100MHz, Rs = 50Ω
FC = 18MHz, DACS = 127
Min.
–
Typ.
2
Max. Unit
7 mVrms
–
1.2
5 mVrms
–
4.6
7 mVrms
–
2
5 mVrms
0.5
–
–
mA
2.0
–
–
mA
–
–
200
Ω
Note: FBDAC is value of boost DAC (i.e., no boost)
Filter Control Characteristics (RX = 12KΩ)
VRX
Reference Current Set Output
Voltage
Tamb = 27°C
(**)
FREQUENCY SYNTHESIZER CHARACTERISTICS (RR = 39KΩ)
–
1.5
–
V
FIN
Input Frequency
8
20 MHz
FOUT Output Frequency
–
96 MHz
JFO
FOUT jitter
TO = 1/FO; Fout = 30MHz
–
±400 ps(pk)
M Divide Number
80
255
–
TVCO
N Divide Number
VCO Center Frequency Period
TO = (9.65 + 0.843 x DR)-1
FLTR1-FLTR1 = 0 (***)
25
0.9TO
127
–
1.1TO ns
VCO Frequency Dynamic
Range
–1.5 ≤ FLTR1-FLTR1 ≤ +1.5,
25
Fout = 54.0MHz (***)
±45
%
KVCO
KD
VCO Control Gain
Phase Detector Gain
ω = 2π/TVCO
–1.5 ≤ FLTR1-FLTR1 ≤ +1.5
KD = 0.7 + 0.43 x DR (***)
0.14ωo
0.83KD
0.26ωo rad/(V-s)
1.17KD µA/rad
KVCO x KD Product Accuracy
– 28
+ 28
%
Reference Clock Characteristics:
Reference Clock Low Time
20
–
ns
Reference Clock High Time
20
–
ns
DATA SEPARATOR DYNAMIC CHARACTERISTICS AND TIMING (Unless otherwise specified, rec-
ommended operating conditions apply.)
Real Mode
TRRC
TFRC
TNS, TNH
TPNRZ
Read Clock Rise Time
Read Clock Fall time
RRC Duty Cycle
NRZ(out) Set Up and Hold Time
NRZ (out) Propagation Delay
0.8V to 2.0V, CL ≤ 15pF
2.0V to 0.8V, CL ≤ 15pF
DR = 32Mbit/s
DR ≤ 20Mbit/s (**)
DR > 20Mbit/s (**)
(**)
(**) Bench test only.
(***) Preliminary data.
–
–
43
15.5
13
–
8
ns
5
ns
57
%
–
ns
–
ns
±15
ns
12/24
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