L6000 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6000' PDF : 24 Pages View PDF
L6000
The internal register map for the serial port is shown below:
Address Bits
Blk Diagr.
Address
Symbol
Function
LSB
MSB
0123456
0100000
1100000
1101000
0101000
0100100
0101100
0110000
0111000
0010000
1010000
1011000
0011000
R02
R03
R0B
R0A
R12
R1A
R06
R0E
R04
R05
R0D
R0C
PD
FCutoff
FBoost
DVTH
SVTH
CA
PSNN
PSMM
VCO CENT
WIN SHIFT
WRT PREC
CB
Power Down Mode Control
DACF-Filter cutoff Frequency Control
DACS-Filter Boost Control
Pulse Detector Voltage Threshold Control (Data Read Mode)
Pulse Detector Voltage Threshold Control (Servo Read Mode)
Control A (Pulse Detector, Filter, frequency synthesizer Control)
Counter Value (frequency synthesizer)
Counter Value (frequency synthesizer)
VCO Center Frequency
Window Shift Magnitude,Direction
Write Precomp magnitude
Control B (Data Separator, Endec Control)
The bit map of each register (except CA, CB & PD) is as follows:
FCutoff register
FBoost register
DVTH register
SVTH register
PSN register
PSM register
VCO CENT register
WIN SHIFT register
WRT PREC register
where:
X
X
DEDC
SEDC
X
M7
FSC
TDAC1
X
FC6
FB6
VD6
VS6
N6
M6
DR6
TDAC0
X
FC5
FB5
VD5
VS5
N5
M5
DR5
WSE
X
FC4
FB4
VD4
VS4
N4
M4
DR4
WSD
X
FC3
FB3
VD3
VS3
N3
M3
DR3
WS3
WP3
FC2
FB2
VD2
VS2
N2
M2
DR2
WS2
WP2
X = Unused bit or don’t care bit
DEDC = Enable dual comparator qualifier in Data read mode.
SEDC = Enable dual comparator qualifier in Servo read mode.
FSC = The frequency synthesizer back comparator state
TDAC1 = DAC Testing control bit #1
TDAC0 = DAC Testing control bit #0
FC1
FB1
VD1
VS1
N1
M1
DR1
WS1
WP1
FC0
FB0
VD0
VS0
N0
M0
DR0
WS0
WP0
Control register CA:
Control register CB:
Bit Symbol Function
Bit Symbol Function
0 EPDT Enable Phase Detector (frequency
0
DW
Direct Write (Bypass Endec)
synthesizer)
1
UT
Pump Up (FLTR1 sources current,
1
FLTR1 sinks current) Test mode
GS
Enable Phase Detector Gain
Switching
2
DT
Pump Down (FLTR1 sinks current,
2 READ DATA I/O Pin Input Control
FLTR1 sources current) Test Mode
3
ET
Enable frequency synthesizer Circuit 3
EPDD
Enable Phase Detector (Data
Function
Separator)
4 BYPT Bypass frequency synthesizer Circuit 4
UD
Pump Up (FLTR2 sources current,
Function
FLTR2 sinks current) Test mode
5
PD
TEST Enable Pulse Detector Test
5
DD
Pump Down (FLTR sinks current,
Points, COUT and DOUT
FLTR2 sources current) Test mode
6 FDCT Force AGC Charge Pump into Fast 6
ED
Enable Data Separator Test Point
Decay Mode
Outputs
7
Unused
7
SOF T
Select Soft or Hard Sector Operation
asserted, then the SERIAL CLOCK+ is driven
with the positive edge latching the state of SE-
RIAL DATA. The actual data is latched into each
register in the L6000 when SERIAL ENABLE is
disasserted, so this signal MUST be driven low
16/24
after EACH register write; failure to deassert SE-
RIAL ENABLE before a 17th SERIAL CLOCK+
will erase ( invalidate ) the previous 16 clock cy-
cles. This also precludes SERIAL CLOCK+ from
being a free running clock in the system. The
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