Power bridges
Figure 17. Half bridge configuration
V pump
V Supply
High side
Driver
Control Signals
From SPI
Control
Logic
Low side
Driver
L6460
DCX Phase output
Note:
In this case each half bridge will behave according to the following truth table.
Table 19.
TSD
1
0
0
0
0
0
0
0
0
Half bridge truth table
nReset
Low
power
mode
Enable
X
X
X
0
X
X
1
1
X
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
Current MtrXCtrl
limit
SideA/B
X
X
X
X
X
X
X
X
0
0
0
0
0
1
0
1
1
X
PWM
X
X
X
X
0
1
0
1
X
OUT
Z
Z
Z
Z
Z
0
Z
1
Z
When “low power mode” bit is active the bridges will reduce its biasing thus contributing to
the power saving.
When a current limit event occurs this event will be latched and the bridges will remain in
high impedance state for the off time.
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Doc ID 17713 Rev 1