L6566B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6566B' PDF : 51 Pages View PDF
L6566B
Application information
This function is useful to implement a latched overtemperature protection very easily by
biasing the pin with a divider from VREF, where the upper resistor is an NTC physically
located close to a heating element like the MOSFET, or the transformer. The DIS pin is a
high impedance input, thus it is prone to pick up noise, which might give origin to undesired
latch-off of the device. It is possible to bypass the pin to ground with a small film capacitor
(e.g. 1-10 nF) to prevent any malfunctioning of this kind.
Figure 20. Operation after latched disable activation: timing diagram
DIS
(pin 8)
4.5V
Vcc
(pin 5)
VccON
VccON -0.5
VccOFF
HV generator is turned on
Vccrestart
GD
(pin 4)
Restart is quicker
t
Disable latch is reset here
t
HV generator turn-on is disabled here
t
Vin
Input source is removed here
VHVstart
AC_OK
t
(pin 16)
Vth
t
5.10
Soft-start and delayed latched shutdown upon overcurrent
At device start-up, a capacitor (CSS) connected between the SS pin (14) and ground is
charged by an internal current generator, ISS1, from zero up to about 2 V where it is
clamped. During this ramp, the overcurrent setpoint progressively rises from zero to the
value imposed by the voltage on the VFF pin (15, see Section 5.6: PWM comparator, PWM
latch and voltage feedforward blocks on page 27); MOSFET’s conduction time increases
gradually, hence controlling the start-up inrush current. The time needed for the overcurrent
setpoint to reach its steady state value, referred to as soft-start time, is approximately:
Equation 12
TSS
=
Css
ISS1
Vcsx
(VVFF
)
=
Css
ISS1
⎜⎜⎝⎛1
−
VVFF
3
⎟⎟⎠⎞
During the ramp (i.e. until VSS = 2 V) all the functions that monitor the voltage on pin COMP
are disabled.
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