L6713ATR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
L6713ATR
STMicroelectronics
'L6713ATR' PDF : 64 Pages View PDF
L6713A
12 Voltage positioning
Voltage positioning
12.1
Output voltage positioning is performed by selecting the reference DAC and by
programming the droop function and offset to the reference (See Figure 11). The currents
sourced from DROOP and sunk from VSEN pins cause the output voltage to vary according
to the external RFB and ROFFSET resistor.
The output voltage is then driven by the following relationship:
VOUT = VREF – (RFB + ROFFSET) ⋅ (IDROOP) + (ROFFSET) ⋅ (IOFFSET)
VREF
=
⎧
⎨
⎩
VID – 19mV
VID
VR10 - VR11
AMD 6BIT
DROOP function can be disabled as well as the OFFSET: connecting DROOP pin and FB
pin together implements the load regulation dependence while, if this effect is not desired,
by shorting DROOP pin to SGND it is possible for the device to operate as a classic voltage
mode buck converter. The DROOP pin can also be connected to SGND through a resistor
obtaining a voltage proportional to the delivered current usable for monitoring purposes.
OFFSET can be disabled by using ROFFSET equal to zero.
Figure 11. Voltage positioning (left) and droop function (right)
VPROG
VREF
ERROR AMPLIFIER
GND DROP
RECOVERY
VMAX
ESR Drop
IOFFSET
IDROOP
VNOM
FBG
VSEN
DROOP
ROFFSET
RFB
To GND_core
(Remote Sense)
To VCC_core
(Remote Sense)
FB
COMP
RF
CF
CP
VMIN
RESPONSE WITHOUT DROOP
RESPONSE WITH DROOP
Offset (Optional)
The IOFFSET current (See Table 5) sunk from the VSEN pin allows programming a positive
offset (VOS) for the output voltage by connecting a resistor ROFFSET between VSEN pin and
VOUT, as shown in the Figure 11; this offset has to be considered in addition to the one
already introduced during the production stage for the Intel VR10,VR11 mode.
The output voltage is then programmed as follow:
VOUT = VREF – (RFB + ROFFSET) ⋅ (IDROOP) + (ROFFSET) ⋅ (IOFFSET)
Offset resistor can be designed by considering the following relationship:
ROFFSET
=
------V----O----S-------
IOFFSET
Offset automatically given by the DAC selection differs from the offset implemented through
the IOFFSET current: the built-in feature is trimmed in production and assures ± 0.5 % error
(± 0.6 % for the AMD DAC) over load and line variations.
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