L6713ATR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
L6713ATR
STMicroelectronics
'L6713ATR' PDF : 64 Pages View PDF
L6713A
14 Dynamic VID transitions
Dynamic VID transitions
The device is able to manage dynamic VID Code changes that allow output voltage
modification during normal device operation. OVP and UVP signals (and PGOOD in case of
AMD mode) are masked during every VID transition and they are re-activated after the
transition finishes with a 32 clock cycles delay to prevent from false triggering due to the
transition.
When changing dynamically the regulated voltage (D-VID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current ID-VID needs to
be delivered, especially when increasing the output regulated voltage and it must be
considered when setting the over current threshold. This current can be estimated using the
following relationships:
ID – VID
=
COUT
⋅
d----V----O----U----T-
dTVID
where dVOUT is the selected DAC LSB (6.25 mV for VR11 and VR10 Extended DAC or
25 mV for AMD DAC) and TVID is the time interval between each LSB transition (externally
driven). Overcoming the OC threshold during the dynamic VID causes the device to enter
the constant current limitation slowing down the output voltage dV/dt also causing the failure
in the D-VID test.
L6713A checks for VID code modifications (See Figure 14) on the rising edge of an internal
additional DVID-clock and waits for a confirmation on the following falling edge. Once the
new code is stable, on the next rising edge, the reference starts stepping up or down in LSB
increments every VID-clock cycle until the new VID code is reached. During the transition,
VID code changes are ignored; the device re-starts monitoring VID after the transition has
finished on the next rising edge available. VID-clock frequency (FDVID) depends on the
operative mode selected: for Intel mode it is in the range of 1 MHz to assure compatibility
with the specifications while, for AMD mode, this frequency is lowered to about 250 kHz.
When L6713A performs a D-VID transition in AMD mode, DVID pin is pulled high as long as
the device is performing the transition (also including the additional 32 clocks delay)
Warning:
Warning: if the new VID code is more than 1 LSB different
from the previous, the device will execute the transition
stepping the reference with the DVID-clock frequency FDVID
until the new code has reached: for this reason it is
recommended to carefully control the VID change rate in
order to carefully control the slope of the output voltage
variation especially in Intel mode.
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