L9347DIE1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L9347DIE1' PDF : 21 Pages View PDF
L9347
against recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage
and invert the status output information.
1.6 Error Detection
The status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON).
If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All ex-
ternal errors, for example open load, are filtered internally. The following table shows the detected errors, the
filter times and the detection mode (on/off).
Short circuit of the load
Open load
(under voltage detection)
ON State
EN &IN = HIGH
X
OFF State
EN &IN = LOW
Filter time
tsf
X
tlf
Reset done by
EN & IN = “LOW”
for TD or TDreg
timer TD
Open load
X
(under current detection)
tsf
timer TD
Overtemperature
Power-GND-loss
X
X
X
Signal-GND-loss
Supply-VS-loss
Clock control
X
X
X
X
X
X
Output voltage clamp active
X
(regulated
channels)
tsf
EN & IN = “LOW”
for TD or TDreg
tlf
in on: EN & IN = “LOW”
for TD or TDreg
in off: timer TD
tlf
timer TD
tlf
timer TD
no
in on: EN & IN = “LOW”
for TD or TDreg
in off: timer TD
no
in on: EN & IN = “LOW”
for TD or TDreg
in off: timer TD
EN&IN=low means that at least one between enable and input is low. For the inputs IN=low means also no input
PWM. For the regulator input period longer than TDreg and for the standard channel input period longer thanTD.
A detected error is stored in an error register. The reset of this register is made with a timer TD. With this ap-
proach all errors are present at the status output at least for the time TD.
All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON
condition are stored into an internal “fail” register. The output is then shut off. The register must be reset with a
low signal at the input. A “low signal” means that the input is low for a time longer than TD or TDReg for the re-
ulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode.
Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail register. This type
of error is only delayed with the standard timer tlf function.
Open load is detected for all four channels in on- and off-state.
Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33 * VS the error reg-
ister is set and delayed with TD. A sink current stage pull the output down to ground, with EN high. With EN low
the output is floating in case of openload and the detection is not assured. In the ON state the load current is
monitored by the non-regulated channels. If it drops below the specified threshold value IQU an open load is
detected and the error register is set and delayed with TD. A regulated channel detects the open load in the on
state with the current regulator error detection. If the output PWM reaches 90% for a time longer than tRE than
an error occurs. This could happen when no load is connected, the resistivity of the load is too high or the supply
voltage too low. The same error is shown if the regulator is not able to reduce the current in the load in the time
tRE, so the output PWM falls below 10%.
A clock failure (clock loss) is detected when the frequency becomes lower than fCLK,min. All status outputs are
10/21
Share Link: 
