Electrical specifications
L99H01
Table 14. Gate drivers for external PowerMOS
Item Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Drivers for external high-side PowerMOS
14.1
IGHx(on)
Turn on current
(SOURCE stage)
Tj = 25 °C (1)
0.3
0.5(2)
0.8
A
14.2.1
14.2.2
14.3
14.4
RGHx
VGHxH
RGSHx
On-resistance of
SINK stage
Gate on voltage
Passive Gate
clamp resistance
VSHx = 0 V; IGHx = 50 mA;
Tj = 25°C
3
4
5
W
VSHx = 0 V; IGHx = 50 mA;
Tj = 125°C
4.5
5.3
7
W
Outputs floating
VSHx + 8 V VSHx + 10 V VSHx + 12 V V
11
13
15
kΩ
Drivers for external low-side PowerMOS
14.5
IGLx(on)
Turn on current
(SOURCE stage)
Tj = 25°C (1)
0.3
0.5(2)
0.8
A
14.6.1
14.6.2
14.7
14.8
RGLx
VGLxH
RGSLx
On-resistance of
SINK stage
Gate on voltage
Passive gate
clamp resistance
VSLx = 0 V; IGHx = 50 mA;
Tj = 25°C
3
4
5
W
VSLx = 0 V; IGHx = 50 mA;
Tj = 125°C
4.5
5.3
7
W
VSLx + 8 V VSLx + 10 V VSLx + 12 V V
11
13
15
kΩ
Timing of the drivers
14.9
tGHxHL
Propagation delay VVS = 13.5 V; VSHx = 0;
time high to low RG = 30 Ω; CG = 4.7 nF
0.8
1.4
1.9
µs
14.10
tGLxHL
Propagation delay VVS = 13.5 V; VSLx = 0;
time low to high RG = 30 Ω,; CG = 4.7 nF
0.6
1.2
1.8
µs
14.11 tGHxr2 Rise time
VVS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 4.7 nF
45
170
ns
14.12 tGHxf2 Fall time
VVS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 4.7 nF
60
210
ns
14.13 tGLxr2 Rise time
VVS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 4.7 nF
45
170
ns
14.14 tGLxf2 Fall time
VVS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 4.7 nF
60
210
ns
1. Indirect measurement, parameter measured dynamically using 100 nF load capacitor and evaluating the slew rate.
2. Average value.
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