LF3310QC15 View Datasheet(PDF) - LOGIC Devices
Part Name
Description
MFG CO.
'LF3310QC15' PDF : 21 Pages View PDF
DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
HLD goes LOW, the Horizontal LF
InterfaceTM is enabled for data input.
The first value fed into the interface
on HCF11-0 is an address which
determines what the interface is going
to load. The three most significant
bits (HCF11-9) determine if the LF
InterfaceTM will load coefficient banks
or Configuration/Control Registers
(see Table 8). The nine least signifi-
cant bits (HCF8-0) are the address for
whatever is to be loaded (see
Tables 9-14). For example, to load
address 15 of the horizontal coefficient
banks, the first data value into the
LF InterfaceTM should be 00FH. To
load horizontal limit register 10, the
first data value should be C0AH. The
first address value should be loaded into
the interface on the same clock cycle that
latches the HIGH to LOW transition of
HLD (see Figures 12 and 13).
The next value(s) loaded into the
interface are the data value(s) which
will be stored in the bank or register
defined by the address value. When
loading coefficient banks, the inter-
face will expect eight values to be
loaded into the device after the
address value. The eight values are
coefficients 0 through 7. When
loading select or Configuration
Registers, the interface will expect one
value after the address value. When
loading round registers, the interface
will expect four values after the
address value. When loading limit
registers, the interface will expect two
values after the address value.
Figures 12 and 13 show the data
loading sequences for the coefficient
banks and Configuration/Control
Registers.
Both HPAUSE and VPAUSE allow the
user to effectively slow the rate of data
loading through the LF InterfaceTM.
When HPAUSE is HIGH, the LF
InterfaceTM affecting the data used for
the Horizontal Filter is held until
HPAUSE is returned to a LOW.
When VPAUSE is HIGH, the LF
InterfaceTM affecting the data used for
the Vertical Filter is held until
VPAUSE is returned to a LOW.
Figures 14 through 17 display the
effects of both HPAUSE and VPAUSE
while loading coefficient and control
data.
Table 15 shows an example of loading
data into the coefficient banks. The
following data values are written into
address 10 of coefficient banks 0
through 7: 210H, 543H, C76H, 9E3H,
701H, 832H, F20H, 143H. Table 16
FIGURE 14. COEFFICIENT BANK LOADING SEQUENCE WITH HPAUSE AND VPAUSE IMPLEMENTATION
COEFFICIENT SET 1
CLK
HPAUSE/VPAUSE
HLD/VLD
HCF/VCF11-0
ADDR1
COEF0
COEF1
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W1
COEF7
FIGURE 15. CONFIGURATION AND SELECT REGISTER LOADING SEQUENCE WITH HPAUSE AND VPAUSE IMPLEMENTATION
CONFIGURATION REGISTER
SELECT REGISTER
CLK
HPAUSE/VPAUSE
HLD/VLD
HCF/VCF11-0
ADDR1
W1
DATA1
ADDR2
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W2
DATA1
Video Imaging Products
13
11/08/2001-LDS.3310-H
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