LH28F016LLT-15 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F016LLT-15' PDF : 29 Pages View PDF
16M (1M × 16, 2M × 8) Flash Memory
LH28F016LL
Timing Nomenclature
All 3.3 V system timings are measured from where signals cross 1.5 V. For 5.0 V systems use the standard JEDEC
cross point definitions. Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE tELQV time (t) from CE » (E) going low (L) to the outputs (Q) becoming valid (V)
tOE tGLQV time (t) from OE » (G) going low (L) to the outputs (Q) becoming valid (V)
tACC tAVQV time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS tAVWH time (t) from address (A) valid (V) to WE » (W) going high (H)
tDH tWHDX time (t) from WE » (W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS
A Address Inputs
D Data Inputs
Q Data Outputs
E CE » (Chip Enable)
G OE» (Output Enable)
W WE (Write Enable)
P RP » (Deep Power-Down Pin)
R RY »/BY » (Ready/Busy)
V Any Voltage Level
3 V VCC at 3.0 V Min.
PIN STATES
H High
L Low
V Valid
X Driven, but not necessarily valid
Z High Impedance
3.0
INPUT 1.5
0.0
TEST POINTS
1.5 OUTPUT
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a
Logic '0'. Input timing begins and output timing ends at 1.5 V.
Input rise and fall times (10% to 90%) < 10 ns.
28F016LLT-6
Figure 6. Transient Input/Output
Reference Waveform (VCC = 3.3 V)
2.5 ns OF 50 Ω TRANSMISSION LINE
FROM OUTPUT
UNDER TEST
TEST
POINT
TOTAL CAPACITANCE = 50 pF
28F016LLT-7
Figure 7. Transient Equivalent Testing
Load Circuit (VCC = 3.3 V)
15
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