LH28F320S5HB-L12 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F320S5HB-L12' PDF : 61 Pages View PDF
sharp
LHF32K10
32
5.5 VCC, VPP, RP# Transitions
Block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed if
VPP falls outside of a valid VPPH1 range, VCC falls
outside of a valid VCC1/2 range, or RP#=VIL. If VPP
error is detected, status register bit SR.3 is set to "1"
along with SR.4 or SR.5, depending on the attempted
operation. If RP# transitions to VIL during block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration, STS(if set to RY/BY# mode)
will remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to VIL
clear the status register.
The CUI latches commands issued by system
software and is not altered by VPP or CE# transitions
or WSM actions. Its state is read array mode upon
power-up, after exit from deep power-down or after
VCC transitions below VLKO.
After block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration, even after VPP
transitions down to VPPLK, the CUI must be placed in
read array mode via the Read Array command if
subsequent access to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block and full chip erasure, (multi)
word/byte writing or block lock-bit configuration during
power transitions. Upon power-up, the device is
indifferent as to which power supply (VPP or VCC)
powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit writes.
The CUI’s two-step command sequence architecture
provides added level of protection against data
alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP#=VIL regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is retained
when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can
consume negligible power by lowering RP# to VIL
standby or sleep modes. If access is again needed,
the devices can be read following the tPHQV and
tPHWL wake-up cycles required after RP# is first
raised to VIH. See AC Characteristics Read Only
and Write Operations and Figures 17, 18, 19, 20 for
more information.
Rev. 1.55
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