LH28F320S5HB-L12 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F320S5HB-L12' PDF : 61 Pages View PDF
sharp
LHF32K10
40
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS(1)
Versions(5)
VCC=5V±0.5V, 5V±0.25V, TA=0°C to +70°C
VCC=5V±0.25V LH28F320S5-L90(6)
VCC=5V±0.5V
LH28F320S5-
L100(7)
Sym.
Parameter
Notes Min.
Max.
Min.
Max.
Unit
tAVAV
tPHWL
Write Cycle Time
RP# High Recovery to WE# Going
Low
90
2
1
100
ns
1
µs
tELWL CE# Setup to WE# Going Low
10
10
ns
tWLWH WE# Pulse Width
40
40
ns
tSHWH WP# VIH Setup to WE# Going High
2
100
100
ns
tVPWH VPP Setup to WE# Going High
2
100
100
ns
tAVWH Address Setup to WE# Going High
3
40
40
ns
tDVWH Data Setup to WE# Going High
3
40
40
ns
tWHDX Data Hold from WE# High
5
5
ns
tWHAX Address Hold from WE# High
5
5
ns
tWHEH CE# Hold from WE# High
10
10
ns
tWHWL WE# Pulse Width High
30
30
ns
tWHRL WE# High to STS Going Low
90
90
ns
tWHGL Write Recovery before Read
0
0
ns
tQVVL VPP Hold from Valid SRD, STS High Z 2,4
0
0
ns
tQVSL WP# VIH Hold from Valid SRD, STS
High Z
2,4
0
0
ns
NOTES:
1. Read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit
configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration.
4. VPP should be held at VPPH1 until determination of block erase, full chip erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 1.55
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