LH28F400SUT-NC80 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F400SUT-NC80' PDF : 35 Pages View PDF
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SU-NC
START
READ COMPATIBLE
STATUS REGISTER
CSR.7 = 0
1
RESET WP
READ COMPATIBLE
STATUS REGISTER
CSR.7 = 0
1
WRITE 77H
WRITE D0H AND
BLOCK ADDRESS
READ COMPATIBLE
STATUS REGISTER
0
CSR.7 =
BUS
OPERATION
COMMAND
COMMENTS
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Write
Reset
After Write D = 47H A = X,
Write Protect Write D = D0H A = 0FFH
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Write
Lock Block D = 77H
A=X
Write
Confirm
D = D0H
A = BA
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Write
Set
After Write D = 57H A = X,
Write Protect Write D = D0H A = 0FFH
NOTE:
See CSR Full Status Check for Data-Write operation.
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Definitions for description of codes.
1
1 (NOTE)
CSR.4, 5 =
0
LOCK
ANOTHER
YES
BLOCK?
NO
SET WP
OPERATION COMPLETE
Figure 9. Block Locking Scheme
28F400SUT-NC60-7
13
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