LH28F800SGHB-L10 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F800SGHB-L10' PDF : 45 Pages View PDF
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.7 RESET OPERATIONS
VOH
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
VOH
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
tPLPH
(A) Reset During Read Array Mode
tPLRH
tPLPH
(B) Reset During Block Erase, Word Write, or Lock-Bit Configuration
2.7 V/3.3 V/5 V
VCC
VIL
VIH
RP# (P)
VIL
t235VPH
(C) VCC Rising Timing
Fig. 16 AC Waveform for Reset Operation
Reset AC Specifications (NOTE 1)
SYMBOL
PARAMETER
VCC = 2.7 to 3.6 V
NOTE MIN.
MAX.
VCC = 5.0±0.5 V
MIN.
MAX. UNIT
RP# Pulse Low Time (If RP# is tied to VCC,
tPLPH
100
this specification is not applicable)
100
ns
RP# Low to Reset during Block Erase,
tPLRH
2, 3
Word Write or Lock-Bit Configuration
20
28 (2.7 V VCC)
12
µs
VCC 2.7 V to RP# High
t235VPH VCC 3.0 V to RP# High
4
100
100
ns
VCC 4.5 V to RP# High
NOTES :
1. These specifications are valid for all product versions
(packages and speeds).
2. If RP# is asserted while a block erase, word write, or
lock-bit configuration operation is not executing, the reset
will complete within 100 ns.
3. A reset time, tPHQV, is required from the latter of RY/BY#
or RP# going high until outputs are valid.
4. When the device power-up, holding RP#-low minimum
100 ns is required after VCC has been in predefined
range and also has been in stable there.
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