512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA
tRWS
R/WA
t ES t EH
tES t EH
t ES
ENA
tRQS tRQH
tRQS tRQH
tRQS
REQA
t RSH
t RSS
t RS
RT2
t RSH
t RSS
CK B
tRWS
R/WB
t ES t EH
t ES t EH
t ES
ENB
tRQS tRQH
tRQS tRQH
tRQS
REQB
NOTES:
1. tRSS and tRSH need not be met unless a rising edge of CKA or CKB occurs while that clock is enabled.
2. tRSS is the time needed to deassert RT2 before returning to a normal FIFO cycle.
3. tRSH is the time needed before asserting RT2 after a normal FIFO cycle.
4. Read and write operations to FIFO #2 should be disabled while RT2 is being asserted.
Figure 29. FIFO #2 Retransmit
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