LH543611P-30 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543611P-30' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA (CKB)
tRWS tRWH
R/WA (R/WB)
ENA (ENB)
tES
tEH
tRQS tRQH
REQA (REQB)
tEF
tSKEW2 (4)
tEF
EF2 (EF1)
CKB (CKA)
tRWS tRWH
R/WB (R/WA)
tES
tEH
ENB (ENA)
tRQS tRQH
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Empty Flags is controlled by rising clock
edges; whereas, internal deassertion of the Empty Flags
is controlled by falling clock edges, and their external deassertion
is controlled by rising clock edges.
4. tSKEW2 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for EF to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW2,
then it is not guaranteed that EF will change state until the next
following CKA (CKB) edge.
Figure 19. Empty Flag Timing, When Synchronous
LH543611/21
543611-44
31
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