LH543611P-30 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543611P-30' PDF : 57 Pages View PDF
LH543611/21
TIMING DIAGRAMS (cont’d)
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
CKA (CKB)
tRWS tRWH
R/WA (R/WB)
ENA (ENB)
tES
tEH
tRQS tRQH
REQA (REQB)
tHF
tSKEW1 (4)
tHF
HF1 (HF2)
CKB (CKA)
tRWS tRWH
R/WB (R/WA)
tES
tEH
ENB (ENA)
tRQS tRQH
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Both assertion and deassertion of the Half-Full Flags are
controlled entirely by rising clock edges, rather than by falling clock edges.
4. tSKEW1 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for HF to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW1,
then it is not guaranteed that HF will change state until the next
following CKA (CKB) edge.
Figure 28. Half-Full Flag Timing, When Synchronized
to a Port Clock Doing Writing
543611-49
40
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