LH543611P-30 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543611P-30' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
Table 5. Control-Register Format
COMMAND
PORT REGISTER
BITS
CODE
VALUE FLAG
AFTER AFFECTED,
RESET IF ANY
A, B
00
L
H PFA, PFB
H
A
L
01
L
β
H
L
02
L
PFA
H
L
03
L
EF2
H
L
04
L
AE2
H
LL
05, 06
LH
LL
HF1
HL, HH
L
07
L
AF1
H
L
08
L
FF1
H
L
09
L
PFB
H
L
10
L
β
H
B
11
L
L
PFB
H
L
12
L
EF1
H
L
13
L
AE1
H
LL
14, 15
LH
LL
HF2
HL, HH
DESCRIPTION
EVEN parity in effect.
ODD parity in effect.
Disable Port A parity generation.
Enable Port A parity generation.
Port A parity-error flag operates
βflowthrough.β
Port A parity-error flag is latched
by CKA.
Set by β CKA, reset by β CKB.
Set and reset by β CKA.
Set by β CKA, reset by β CKB.
Set and reset by β CKB.
Set by β CKA, reset by β CKB.
Set and reset by β CKB.
Set and reset by β CKA.
Set by β CKA, reset by β CKB.
Set and reset by β CKA.
Set by β CKA, reset by β CKB.
Set and reset by β CKA.
Parity check computed over all
four bytes of each word.
Parity check computed over half-
word or single-byte according to
WS1 β WS0 setting.
Disable Port B parity generation.
Enable Port B parity generation.
Port B parity-error flag operates
βflowthroughβ.
Port B parity-error flag is latched
by CKB.
Set by β CKB, reset by β CKA.
Set and reset by β CKB.
Set by β CKB, reset by β CKA.
Set and reset by β CKA.
Set and reset by β CKA.
Set and reset by β CKA.
Set and reset by β CKA.
NOTES
A correct 9-bit byte has an even
number of ones.
A correct 9-bit byte has an odd number
of ones.
No overwriting of parity bits.
Parity bit over eight least-significant bits
of each byte is overwritten into the
most-significant bit of that byte.
PFA is subject to transient glitches
while data bus is changing.
PFA is subject to transient glitches
while data bus is changing.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking by
Port B clock.
Synchronous flag clocking by
Port A clock.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking.
Full-word parity-error indication
regardless of WS1 β WS0 setting.
Full-word, half word, or single-byte
parity-error indication according to
WS1 β WS0 setting.
No overwriting of parity bits.
Parity bit over eight least-significant bits
of each byte is overwritten into the
most-significant bit of that byte.
PFB is subject to transient glitches
while data bus is changing.
PFB remains steady until its value
should change.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking by Port A
clock.
Synchronous flag clocking by Port B
clock.
21
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