LH543611/21
TIMING DIAGRAMS (cont’d)
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
RS
t RSS
t RSH
CKA
R/WA
ENA
REQA
tRWS
t RWH
t ES
t EH
t RQS
t RQH
tRWS
t RWH
t ES
t EH
tRQS
tRQH
OEB
t BS
t BH
tA
tBA
t ZX
t OH
D0B - D35B
BYPASS IN
BYPASS DATA OUT
OEA
tBA
tOH
tBS tBH
t XZ
D0A - D35A
PREVIOUS DATA
BYPASS
OUT
BYPASS
IN
NOTES:
1. tRSS, tRSH need not be met unless the rising edge of CKA or CKB occurs while that clock is enabled.
2. Port A is considered the master port for bypass operation. Thus, CKA, R/WA, ENA, and REQA control
the transmission of data between ports at reset.
Figure 12. Data Bypass Timing
543611-20
24