LH543611P-30 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543611P-30' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA
WRITE TO
MAILBOX #1
tRWS tRWH
READ FROM
MAILBOX #2
tRWS tRWH
R/WA
t ES
t EH
t ES
t EH
ENA
tRQS
tRQH
tRQS
tRQH
REQA
t AS
t AH
t AS
t AH
A2A
A1A
A0A
MBF2
CKB
t AS
t AH
t AS
t AH
t AS
t AH
t AS
t AH
MAXIMUM OF 2 CKB
CYCLES LATENCY
tMBF
tMBF
MBF1
OEA
t DS
t DH
tA
t ZX
tA
t OH
D0A - D35A
MAILBOX IN
NOTES:
1. Both edges of MBF2 are synchronized to the Port A clock, CKA.
2. Both edges of MBF1 are synchronized to the Port B clock, CKB.
3. There is a maximum of two CKB clock cycles of synchronization latency before MBF1
is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.
Figure 15. Port A Mailbox Access
MAILBOX OUT
LH543611/21
543611-23
27
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