LH543611P-30 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543611P-30' PDF : 57 Pages View PDF
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKB
R/WB
READ FROM
READ FROM
FIFO #1
tCC
FIFO #1
tCC
WRITE TO
FIFO #2
tCH
tCL
tCH
tCL
tRWS
tRWH
tRWS
t RWH
tRWS tRWH
tES
tEH
tES
tEH
t ES
t EH
ENB
REQB
A0B
tRQS
tRQH
tAS
tAH
tRQS
tRQH
tAS
tAH
tRQS tRQH
tAS
tAH
OEB
tA
tZX
tA
tOH
tA
tOH
D0B - D35B
ASYNCHRONOUS
PFB
PREVIOUS
DATA N1
t PF
DATA OUT N2
tPF
VALID PF
FOR N1
tPF
VALID PF FOR N2
tPF
SYNCHRONOUS
PFB
VALID PF FOR N1
tXZ
tDS
tDH
DATA OUT
N3
tPF
DATA IN N4
tPF
VALID PF
FOR N3
VALID PF
FOR N4
tPF
VALID PF FOR N2
VALID PF FOR N4
NOTES:
1. The Port B Parity Error Flag (PFB) reflects the parity status of data present
on the data bus, after a delay tPF, when operated asynchronously.
2. The Port B Parity Error Flag (PFB) reflects the parity status of data present
on the data bus during the previous clock cycle, and meeting the setup
time at CKB, when operated synchronously.
3. The status of OEB does not gate read or write operations.
4. If OEB is left LOW during a write operation, then the previous data held in
the output latch is written back into FIFO #2.
Figure 14. Port B FIFO Read/Write
543611-22
26
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