LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
Table 5. Control-Register Format (contโd)
COMMAND
PORT REGISTER
BITS
16
B
17
CODE
L
H
L
H
VALUE FLAG
AFTER AFFECTED,
RESET IF ANY
L
AF2
L
FF2
DESCRIPTION
Set by โ CKB, reset by โ CKA.
Set and reset by โ CKB.
Set by โ CKB, reset by โ CKA.
Set and reset by โ CKB.
NOTES
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking.
Table 6. Controllable Functions
TYPE
Parity
DESCRIPTION
Even/Odd
Policy for 9/18-Bit Word-Width Selection
Generation: Enable/Disable
CONTROL-REGISTER BIT
PORT A
01
PORT B
01
โ
9
1
10
Flag Behavior: Latched/Flowthrough
2
11
EF Synchronous/Asynchronous
3
12
AE Synchronous/Asynchronous
4
Flag Synchronization HF Synchronous-With-Write/Synchronous-With-Read
5โ6
13
14โ15
AF Synchronous/Asynchronous
7
16
FF Synchronous/Asynchronous
8
17
NOTE:
1. LH5420/LH543601 also have this Control-Register function. The same Control-Register bit, bit 00, controls both Port A and Port B functionality.
A
B
PARITY
E
V
E
N
O
D
D
35
10
LH5420/LH543601 CONTROL REGISTER (WRITE-ONLY)
(FOR COMPARISON PURPOSES)
35
22
PORT B
FLAG
SYNCHRONIZATION
PARITY
PORT A
FLAG
SYNCHRONIZATION
A
B
PARITY
P
E
L
O
L
V
A PL
AP E
TGI
TG N
C EC
CE
H NY
HN O
D
FF2 AF2 HF2 AE1 EF1 PFB B B FF1 AF1 HF1 AE2 EF2 PFA A D
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LH543611/21 CONTROL REGISTER (READ/WRITE)
Figure 10. LH5420/LH543601 and LH543611/21
Control-Register Formats
543611-12