LH543611P-30 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543611P-30' PDF : 57 Pages View PDF
LH543611/21
TIMING DIAGRAMS (cont’d)
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
CKB
R/WB
ENB
REQB
A0B
MBF1
CKA
MBF2
WRITE TO
MAILBOX #2
tRWS tRWH
READ FROM
MAILBOX #1
tRWS tRWH
t ES
t EH
tRQS
tRQH
t ES
t EH
tRQS
tRQH
t AS
t AH
t AS
t AH
MAXIMUM OF 2 CKA
CYCLES LATENCY
t MBF
t MBF
OEB
t DS
t DH
tA
tA
t ZX
t OH
D0B - D35B
MAILBOX IN
NOTES:
1. Both edges of MBF2 are synchronized to the Port A clock, CKA.
2. Both edges of MBF1 are synchronized to the Port B clock, CKB.
3. There is a maximum of two CKA clock cycles of synchronization latency before MBF2
is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.
Figure 16. Port B Mailbox Access
MAILBOX OUT
543611-24
28
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