LH543611/21
TIMING DIAGRAMS (cont’d)
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
CKA (CKB)
tRWS tRWH
R/WA (R/WB)
t ES
t EH
ENA (ENB)
tRQS
tRQH
REQA (REQB)
t HF
t HF
HF1 (HF2)
CKB (CKA)
tRWS tRWH
R/WB (R/WA )
ENB (ENA)
t ES
t EH
tRQS
tRQH
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Both assertion and deassertion of the Half-Full Flags are controlled
entirely by rising clock edges, rather than by falling clock edges.
Figure 26. Half-Full Flag Timing, When Asynchronous
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