sharp
LHF16KAP
43
6.2.7 RESET OPERATIONS
High Z
STS(R)
VOL
VIH
RP#(P)
VIL
High Z
STS(R)
VOL
VIH
RP#(P)
VIL
tPLPH
(A)Reset During Read Array Mode
tPLRH
tPLPH
(B)Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuretion
VCC
RP#(P)
5V
VIL
t5VPH
VIH
VIL
(C)VCC Power Up Timing
Figure 21. AC Waveform for Reset Operation
Reset AC Specifications
Symbol
Parameter
Notes
VCC=5V
Min.
Max.
Unit
tPLPH
RP# Pulse Low Time
(If RP# is tied to VCC, this specification is not applicable)
100
tPLRH RP# Low to Reset during Block Erase, Full Chip Erase,
(Multi) Word/Byte Write or Block Lock-Bit Configuration
1,2
ns
13.1
µs
t5VPH VCC at 4.5V to RP# High
NOTES:
3
100
ns
1. If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration
operation is not executing, the reset will complete within 100ns.
2. A reset time, tPHQV, is required from the latter of STS going High Z or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range
and also has been in stable there.
Rev. 2.0