LHF32KZ5 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LHF32KZ5' PDF : 66 Pages View PDF
sharp
LHF32KZ5
9
3 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, query structure, or status register independent
of the VPP voltage. RP# must be at VIH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, Query
or Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-down
mode, the device automatically resets to read array
mode. Five control pins dictate the data flow in and
out of the component: BE# (BE0#, BE1L#, BE1H#),
OE#, WE#, RP# and WP#. BE0#, BE1L#, BE1H# and
OE# must be driven active to obtain data at the
outputs. BE0#, BE1L#, BE1H# is the device selection
control, and when active enables the selected
memory device. OE# is the data output (DQ0-DQ15)
control and when active drives the selected memory
data onto the I/O bus. WE# and RP# must be at VIH.
Figure 18, 19 illustrates a read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ15 are
placed in a high-impedance state.
3.3 Standby
Either BE0# or BE1L#, BE1H# at a logic-high level
(VIH) places the device in standby mode which
substantially reduces device power consumption.
DQ0-DQ15 outputs are placed in a high-impedance
state independent of OE#. If deselected during block
erase, bank erase, (multi) word/byte write and block
lock-bit configuration, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, bank erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tPHWL is required after RP#
goes to logic-high (VIH) before another command can
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP’s
flash memories allow proper CPU initialization
following a system reset through the use of the RP#
input. In this application, RP# is controlled by the
same RESET# signal that resets the system CPU.
3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer code, device code, block status codes
for each block (see Figure 4). Using the manufacturer
and device codes, the system CPU can automatically
match the device with its proper algorithms. The
block status codes identify locked or unlocked block
setting and erase completed or erase uncompleted
condition.
3.6 Query Operation
The query operation outputs the query structure.
Query database is stored in the 48Byte ROM. Query
structure allows system software to gain critical
information for controlling the flash component.
Query structure are always presented on the lowest-
order data output (DQ0-DQ7) only.
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