LHF32KZ5 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LHF32KZ5' PDF : 66 Pages View PDF
sharp
LHF32KZ5
12
Mode
Read
Output Disable
Standby
Deep Power-Down
Read Identifier
Codes
Query
Write
Table 3. Bus Operations(BYTE#=VIH)
Notes RP# BE0# BE1L# BE1H# OE# WE# Address VPP DQ0-15 STS
Bank0
Bank1
Disable
1,2,3,9,
10
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIL VIL VIH
VIL
X
X DOUT X
3
VIH VIL
VIL
VIL VIH VIH
X
X High Z X
Bank0
VIL
VIH
VIL
Bank1
Bank0,1
3
Bank0,1
VIH
VIL
X
VIH
VIL
VIH
X
VIH
VIH
X
X
X
X
X High Z X
4
VIL
X
X
X XX
X
X High Z High Z
Bank0
VIL
Bank1
Disable
9,10
VIH
VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIL
VIH
See
Figure 4
X Note 5 High Z
9,10 VIH VIL
VIL
VIL
VIL
VIH
See Table
7~11
X
Note 6 High Z
Bank0
VIL
VIL
VIH
Bank1 3,7,8,9 VIH VIL
VIH
VIL VIH VIL
X
Bank0,1
VIL
VIL
VIL
X DIN
X
Mode
Read
Output Disable
Standby
Deep Power-Down
Read Identifier
Codes
Query
Bank0
Bank1
Disable
Bank0
Bank1
Bank0,1
Bank0,1
Bank0
Bank1
Disable
Table 3.1. Bus Operations(BYTE#=VIL)
Notes RP# BE0# BE1L# BE1H# OE# WE# Address VPP
1,2,3,9,
10
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIL VIL VIH
VIL
X
X
3
VIH VIL
VIL
VIL VIH VIH
X
X
VIL
VIH
VIL
3
VIH
VIL
X
VIL
VIH
VIH
VIH
X
X
X
X
VIH
X
X
4
VIL
X
X
X XX
X
X
VIL
9,10 VIH VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIL
VIH
See
Figure 4
X
9,10 VIH VIL
VIL
VIL
VIL
VIH
See Table
7~11
X
DQ0-7
DOUT
High Z
High Z
High Z
Note 5
Note 6
STS
X
X
X
High Z
High Z
High Z
Write
NOTES:
Bank0
VIL
VIL
VIH
Bank1
Bank0,1
3,7,8,9
VIH
VIL
VIL
VIH
VIL
VIL VIH VIL
VIL
X
X DIN
X
1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See DC Characteristics for
VPPLK and VPPH1/2/3 voltages.
3. STS is VOL (if configured to RY/BY# mode) when the WSM is executing internal block erase, bank erase, (multi)
word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy, in block
erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep power-
down mode.
4. RP# at GND±0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, bank erase, (multi) word/byte write or block lock-bit configuration are
reliably executed when VPP=VPPH1/2/3 and VCC=VCC1/2/3/4.
8. Refer to Table 4 for valid DIN during a write operation.
9. Don’t use the timing both OE# and WE# are VIL.
10.Impossible to perform read from both banks at a time. Both BE0# and BE1L#, BE1H# must not be low at the
same time.
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