LHF32KZ5 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LHF32KZ5' PDF : 66 Pages View PDF
sharp
LHF32KZ5
49
6.2.7 RESET OPERATIONS
High Z
STS(R)
VOL
VIH
RP#(P)
VIL
High Z
STS(R)
VOL
VIH
RP#(P)
VIL
tPLPH
(A)Reset During Read Array Mode
tPLRZ
tPLPH
(B)Reset During Block Erase, Bank Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuretion
2.7/3.3/5V
VCC
VIL
VIH
RP#(P)
VIL
t235VPH
(C)VCC Power Up Timing
Figure 22. AC Waveform for Reset Operation
Reset AC Specifications
Symbol
Parameter
VCC=2.7V
Notes Min. Max.
VCC=3.3V
Min. Max.
VCC=5V
Min. Max. Unit
tPLPH RP# Pulse Low Time
(If RP# is tied to VCC, this
100
100
100
ns
specification is not applicable)
tPLRZ RP# Low to Reset during
Block Erase, Bank Erase,
(Multi) Word/Byte Write or
1,2
21.5
21.1
13.1 µs
Block Lock-Bit Configuration
t235VPH VCC at 2.7V to RP# High
VCC at 3.0V to RP# High
3
100
100
100
ns
VCC at 4.5V to RP# High
NOTES:
1. If RP# is asserted while a block erase, bank erase, (multi) word/byte write or block lock-bit configuration
operation is not executing, the reset will complete within 100ns.
2. A reset time, tPHQV, is required from the latter of STS going High Z or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range
and also has been in stable there.
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