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LM3S611 View Datasheet(PDF) - Unspecified

Part Name
Description
MFG CO.
LM3S611
ETC2
Unspecified 
'LM3S611' PDF : 409 Pages View PDF
Architectural Overview
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
False-start-bit detection
Line-break generation and detection
„ ADC
Single- and differential-input configurations
FourSix 10-bit channels (inputs) when used as single-ended inputs
Sample rate of 500 thousand samples/second
Flexible, configurable analog-to-digital conversion
Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
„ I2C
Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
Interrupt generation
Master with arbitration and clock synchronization, multimaster support, and 7-bit
addressing mode
„ PWM
Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM
generator, and a dead-band generator
One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
Two comparators
• Comparator value updates can be synchronized
• Produces output signals on match
PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter
and comparator output signals
• Produces two independent PWM signals
Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving
a half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
Flexible output control block with PWM output enable of each PWM signal
24
April 27, 2007
Preliminary
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