LPC1776 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1776
NXP Semiconductors.
'LPC1776' PDF : 117 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
[1] PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating
pins, if not used, should be tied to ground or power to minimize power consumption.
[2] I = Input; O = Output; OL = Output driving LOW; G = Ground; S = Supply.
[3] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL
levels and hysteresis.
[4] 5 V tolerant standard pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with
TTL levels and hysteresis. This pad can be powered by VBAT.
[5] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present or configured for an analog function, do not exceed 3.6 V)
providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the
pad is disabled.
[6] 5 V tolerant fast pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL
levels and hysteresis.
[7] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present or configured for an analog function, do not exceed 3.6 V)
providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the
pad is disabled.
[8] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0
(Full-speed and Low-speed mode only).
[10] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) with 5 ns glitch filter providing digital I/O
functions with TTL levels and hysteresis.
[11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[12] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) with 20 ns glitch filter providing digital I/O
function with TTL levels and hysteresis.
[13] This pad can be powered from VBAT.
[14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can’t be
used to drive the RTCX1 pin.
[15] If the RTC is not used, these pins can be left floating.
[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
Table 4. Pin allocation table TFBGA208
Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
Ball Symbol
Ball Symbol
Ball Symbol
Row A
1
P3[27]
5
P1[4]
2
VSS
6 P1[9]
3 P1[0]
7 P1[14]
9
P1[17]
10 P1[3]
11 P4[15]
13 P3[20]
14 P1[11]
15 P0[8]
17 P1[5]
-
-
Row B
1
P3[2]
2 P3[10]
3 P3[1]
5
P1[1]
9
P4[25]
6
VSS
10 P4[29]
7 P4[30]
11 P1[6]
13
VDD(3V3)
17 P2[0]
14 P3[19]
-
15 P4[14]
-
Row C
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
Ball Symbol
4 P4[31]
8 P1[15]
12 VSS
16 P1[12]
-
4 P3[0]
8 P4[24]
12 P0[4]
16 P4[13]
-
© NXP Semiconductors N.V. 2016. All rights reserved.
35 of 126
Share Link: 