LPC1777 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1777
NXP Semiconductors.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
7.7 Memory map
Table 6. LPC178x/177x memory usage and details
Address range General Use
Address range details and description
0x0000 0000 to On-chip non-volatile 0x0000 0000 - 0x0007 FFFF
0x1FFF FFFF memory
0x0000 0000 - 0x0003 FFFF
For devices with 512 kB of flash memory.
For devices with 256 kB of flash memory.
0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory.
0x0000 0000 - 0x0000 FFFF For devices with 64 kB of flash memory.
On-chip main SRAM 0x1000 0000 - 0x1000 FFFF For devices with 64 kB of main SRAM.
0x1000 0000 - 0x1000 7FFF For devices with 32 kB of main SRAM.
0x1000 0000 - 0x1000 3FFF For devices with 16 kB of main SRAM.
Boot ROM
0x1FFF 0000 - 0x1FFF 1FFF 8 kB Boot ROM with flash services.
0x2000 0000 to
0x3FFF FFFF
On-chip SRAM
(typically used for
peripheral data)
0x2000 0000 - 0x2000 1FFF
0x2000 2000 - 0x2000 3FFF
0x2000 4000 - 0x2000 7FFF
Peripheral RAM - bank 0 (first 8 kB)
Peripheral RAM - bank 0 (second 8 kB)
Peripheral RAM - bank 1 (16 kB)
AHB peripherals
0x2008 0000 - 0x200B FFFF See Figure 6 for details
0x4000 0000 to APB Peripherals
0x7FFF FFFF
0x4000 0000 - 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x4008 0000 - 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x8000 0000 to
0xDFFF FFFF
Off-chip Memory via
the External Memory
Controller
Four static memory chip selects:
0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64 MB)
0x9000 0000 - 0x93FF FFFF Static memory chip select 1 (up to 64 MB)
0x9800 0000 - 0x9BFF FFFF Static memory chip select 2 (up to 64 MB)
0x9C00 0000 - 0x9FFF FFFF Static memory chip select 3 (up to 64 MB)
Four dynamic memory chip selects:
0xA000 0000 - 0xAFFF FFFF Dynamic memory chip select 0 (up to 256MB)
0xB000 0000 - 0xBFFF FFFF Dynamic memory chip select 1 (up to 256MB)
0xC000 0000 - 0xCFFF FFFF Dynamic memory chip select 2 (up to 256MB)
0xD000 0000 - 0xDFFF FFFF Dynamic memory chip select 3 (up to 256MB)
0xE000 0000 to Cortex-M3 Private
0xE00F FFFF Peripheral Bus
0xE000 0000 - 0xE00F FFFF Cortex-M3 related functions, includes the NVIC
and System Tick Timer.
The LPC178x/7x incorporate several distinct memory regions, shown in the following
figures. Figure 6 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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