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LPC1777 View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
MFG CO.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.19.1 Features
10-bit DAC.
Resistor string architecture.
Buffered output.
Power-down mode.
Selectable output drive.
Dedicated conversion timer.
DMA support.
7.20 UARTs
Remark: USART4 is not available on part LPC1774FBD144.
The LPC178x/7x contain five UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.20.1 Features
Maximum UART data bit rate of 7.5 MBit/s.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Auto-baud capability.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing.
All UARTs have DMA support for both transmit and receive.
UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
USART4 includes an IrDA mode to support infrared communication.
USART4 supports synchronous mode and a smart card mode conforming to
ISO7816-3.
7.21 SSP serial I/O controller
The LPC178x/7x contain three SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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