LPC1777 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1777
NXP Semiconductors.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.33.1.3 RTC oscillator
The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can
be output on the CLKOUT pin in order to allow trimming the RTC oscillator without
interference from a probe.
7.33.1.4 Watchdog oscillator
The Watchdog Timer has a dedicated watchdog oscillator that provides a 500 kHz clock to
the Watchdog Timer. The watchdog oscillator is always running if the Watchdog Timer is
enabled. The Watchdog oscillator clock can be output on the CLKOUT pin in order to
allow observe its frequency.
In order to allow Watchdog Timer operation with minimum power consumption, which can
be important in reduced power modes, the Watchdog oscillator frequency is not tightly
controlled. The Watchdog oscillator frequency will vary over temperature and power
supply within a particular part, and may vary by processing across different parts. This
variation should be taken into account when determining Watchdog reload values.
Within a particular part, temperature and power supply variations can produce up to a
17 % frequency variation. Frequency variation between devices under the same
operating conditions can be up to 30 %.
7.33.2 Main PLL (PLL0) and Alternate PLL (PLL1)
PLL0 (also called the Main PLL) and PLL1 (also called the Alternate PLL) are functionally
identical but have somewhat different input possibilities and output connections. These
possibilities are shown in Figure 7. The Main PLL can receive its input from either the IRC
or the main oscillator and can potentially be used to provide the clocks to nearly
everything on the device. The Alternate PLL receives its input only from the main oscillator
and is intended to be used as an alternate source of clocking to the USB. The USB has
timing needs that may not always be filled by the Main PLL.
Both PLLs are disabled and powered off on reset. If the Alternate PLL is left disabled, the
USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB
clock through that route. The source for each clock must be selected via the CLKSEL
registers and can be further reduced by clock dividers as needed.
PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only
the Main PLL is used, then its output frequency must be an integer multiple of all other
clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring
an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled
Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional
dividers to bring the output down to the desired frequencies. The minimum output divider
value is 2, insuring that the output of the PLLs have a 50 % duty cycle.
If the USB is used, the possibilities for the CPU clock and other clocks will be limited by
the requirements that the frequency be precise and very low jitter, and that the PLL0
output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the
operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in
conjunction with the PLL can meet the precision and jitter specifications for USB. It is due
to these limitations that the Alternate PLL is provided.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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