LPC47B272-MS View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47B272-MS' PDF : 195 Pages View PDF
The MIDI protocol requires 31.25k Baud (±1%) and 10 bits total per frame: 1 start bit, 8 data bits, no
parity, and 1 stop bit. For example, there are 320 microseconds per serial MIDI data byte. MIDI data is
transferred LSB first (Figure 4).
The UART is configured in full-duplex mode for the MPU-401 MIDI Interface, with 16-byte send/receive
FIFOs.
MIDI RX CLOCK1
MIDI_IN
MIDI RX DATA BYTE (01H)
FIGURE 4 - MIDI DATA BYTE EXAMPLE
NOTE1 MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32µs.
MPU-401 Configuration Registers
The LPC47B27x configuration registers are in Logical Device B (see Configuration section). The
configuration registers contain the MPU-401 Activate, Base Address and Interrupt select. The defaults
for the Base Address and Interrupt Select configuration registers match the MPU-401 factory defaults.
Activate and I/O Base Address
When the Activate bit D0 is ‘0’, the MPU-401 I/O base address decoder is disabled, the IRQ is always
deasserted, and the MPU-401 hardware is in a minimum power-consumption state. When the Activate
bit is ‘1’, the MPU-401 I/O base address decoder and the IRQ are enabled, and the MPU-401 hardware
is fully powered.
Register 0x60 is the MPU-401 I/O Base Address High Byte, register 0x61 is the MPU-401 I/O Base
Address Low Byte. The MPU-401 I/O base address is programmable on even-byte boundaries. The
valid MPU-401 I/O base address range is 0x0100 – 0x0FFE. See Section “Host Interface”.
SMSC LPC47B27x
- 73 -
DATASHEET
Rev. 04-17-07
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