LPC47B272-MS View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47B272-MS' PDF : 195 Pages View PDF
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev
1.14, July 14, 1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is:
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
D7
PD7
Addr/RLE
nBusy
0
D6
PD6
nAck
0
0
compress
0
intrValue
MODE
D5
D4
D3
D2
D1
D0
PD5
PD4
PD3
PD2
PD1
PD0
Address or RLE field
PError
Select
nFault
0
0
0
Direction
ackIntEn SelectIn
nInit
autofd strobe
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
0
1
0
0
0
0
Parallel Port IRQ
Parallel Port DMA
nErrIntrEn dmaEn serviceIntr
full
empty
Note
2
1
1
2
2
2
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the
Configuration Registers.
ECP IMPLEMENTATION STANDARD
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC
devices supporting ECP must meet the requirements contained in this section or the port will not be
supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended
Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is
available from Microsoft.
Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a
standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of
gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high
burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the
maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic
handshake for the standard parallel port to improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is
accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the
next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte
the specified number of times. Hardware support for compression is optional.
NAME
nStrobe
PData 7:0
TYPE
O
I/O
Table 41 - ECP Pin Descriptions
DESCRIPTION
During write operations nStrobe registers data or address into the slave on
the asserting edge (handshakes with Busy).
Contains address or data or RLE data.
SMSC LPC47B27x
- 80 -
DATASHEET
Rev. 04-17-07
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