LPC47B37X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47B37X

100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications

SMSC -> Microchip 

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The following list summarizes the blocks, registers and pins that are powered by VTR.

• PME interface block

• Runtime register block (includes all PME, SMI, GPIO and other miscellaneous registers)

• Wake on Specific Key logic

• LED control logic

• Pins for PME Wakeup:

- GP42/nIO_PME (output, buffer powered by VTR)

- nRI1 (input)

- GP50/nRI2 (input)

- GP52/RXD2/IRRX (input)

- KDAT (input)

- MDAT (input)

- GPIOs (GP10-GP17, GP20-GP27, GP30-GP37, GP41, GP43, GP50-GP57, GP60, GP61)–

all input-only except GP53, GP60, GP61. See below.

• Other Pins

- GP53/TXD2/IRTX (output, buffer powered by VTR)

- GP60/LED1 (output, buffer powered by VTR)

- GP61/LED2 (output, buffer powered by VTR)

Maximum Current Values

See the “Operational Description” section for the maximum current values.

The maximum VTR current, ITR, is given with all outputs open (not loaded). The total maximum current

for the part is the unloaded value PLUS the maximum current sourced by all pins that are driven by

VTR. The pins that are powered by VTR are as follows: GP42/nIO_PME, GP53/TXD2/IRTX,

GP60/LED1, GP61/LED2. These pins, if configured as push-pull outputs, will source a minimum of

6mA at 2.4V when driving.

The maximum VCC current, ICC, is given with all outputs open (not loaded).

Power Management Events (PME/SCI)

The LPC47B37x offers support for Power Management Events (PMEs), also referred to as System

Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this

document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output

signal on pin 17. See the “PME Support” section.

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