LPC47B37X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47B37X
SMSC -> Microchip
'LPC47B37X' PDF : 254 Pages View PDF
FUNCTIONAL DESCRIPTION
Super I/O Registers
Host Processor Interface (LPC)
The address map, shown below in Table 1, shows
the addresses of the different blocks of the Super
I/O immediately after power up. The base
addresses of the FDC, serial and parallel ports,
PME register block, Game port and configuration
register block can be moved via the configuration
registers. Some addresses are used to access
more than one register.
The host processor communicates with the
LPC47B37x through a series of read/write
registers via the LPC interface. The port
addresses for these registers are shown in Table
1. Register access is accomplished through I/O
cycles or DMA transfers. All registers are 8 bits
wide.
Table 1 - Super I/O Block Addresses
LOGICAL
ADDRESS
BLOCK NAME
DEVICE
NOTES
Base+(0-5) and +(7)
Floppy Disk
0
Base+(0-7)
Serial Port Com 1
4
Base+(0-7)
Serial Port Com 2
5
IR Support
Parallel Port
3
Base+(0-3)
SPP
Base+(0-7)
EPP
Base+(0-3), +(400-402)
ECP
Base+(0-7), +(400-402)
ECP+EPP+SPP
60, 64
KYBD
7
Base + (0-6C)
Runtime Registers
A
Base+(0-3)
SMBus
B
Base + (0-1)
Configuration
Note 1: Refer to the configuration register descriptions for setting the base address.
16
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