LPC47B37X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47B37X
SMSC -> Microchip
'LPC47B37X' PDF : 254 Pages View PDF
BIT 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output
signal. Table 7 shows the precompensation values for the combination of these bits settings. Track 0 is
the default starting track number to start precompensation. This starting track number can be changed by
the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy
controller clock and data separator circuits will be turned off. The controller will come out of manual low
power mode after a software reset or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F
in the runtime register block.
Table 7 - Precompensation Delays
PRECOMP
432
111
001
010
011
100
101
110
000
PRECOMPENSATION
DELAY (nsec)
<2Mbps
2Mbps
0.00
0
41.67
20.8
83.34
41.7
125.00
62.5
166.67
83.3
208.33
104.2
250.00
125
Default
Default
Default: See Table 10
28
Share Link: 