LPC47B37X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47B37X

100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications

SMSC -> Microchip 

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Bit 0

This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt

is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a

pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending.

Bits 1 and 2

These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the

Interrupt Control Table.

Bit 3

In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout

interrupt is pending.

Bits 4 and 5

These bits of the IIR are always logic "0".

Bits 6 and 7

These two bits are set when the FIFO CONTROL Register bit 0 equals 1.

FIFO

MODE

ONLY

BIT 3

0

0

0

1

0

INTERRUPT

IDENTIFICATION

REGISTER

BIT 2 BIT 1 BIT 0

0

0

1

1

1

0

1

0

0

1

0

0

0

1

0

Table 29 - Interrupt Control

INTERRUPT SET AND RESET FUNCTIONS

PRIORITY INTERRUPT

INTERRUPT

INTERRUPT

LEVEL

TYPE

SOURCE

RESET CONTROL

-

None

None

-

Highest Receiver Line Overrun Error,

Reading the Line

Status

Parity Error,

Status Register

Framing Error or

Break Interrupt

Second Received Data Receiver Data

Read Receiver

Available

Available

Buffer or the FIFO

drops below the

trigger level.

Second Character

No Characters Reading the

Timeout

Have Been

Receiver Buffer

Indication

Removed From or Register

Input to the RCVR

FIFO during the

last 4 Char times

and there is at

least 1 char in it

during this time

Third

Transmitter Transmitter

Reading the IIR

Holding

Holding Register Register (if Source

Register Empty Empty

of Interrupt) or

Writing the

Transmitter Holding

Register

74

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